Waveform dumps and debugging in Verilog

Waveforms reveal signal changes over time and help trace a failure back through its causes. Dump only the relevant hierarchy for large tests, and pair visual inspection with automated checks. A waveform is evidence of what the model did, not proof that every requirement or input sequence was exercised.

Worked example

The testbench writes a VCD file containing the example scope. Two input changes cause the XOR output to change. Open example.vcd in a waveform viewer after running the simulation and inspect both values and timestamps.

module example;
reg a,b;wire y;
assign y=a ^ b;
initial begin
  $dumpfile("example.vcd");
  $dumpvars(0,example);
  a=0;b=0;#2;a=1;#2;b=1;#2;
  $finish;
end
endmodule

What to watch for

A waveform viewer may display several same-timestamp events at one visual location. Inspect event ordering and simulator logs when a race is suspected.

Try it yourself

Why keep a self-checking test even when a waveform is available?

Answer: It detects regressions automatically and gives a precise pass/fail condition. Manual waveform inspection alone does not scale across changes and parameter combinations.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.