Synthesizable and simulation-only constructs in Verilog

Synthesizable RTL is the subset a particular synthesis flow can translate into hardware. Combinational equations and supported clocked storage patterns are common examples. Simulation-only behavior includes testbench delays, printing and general host file I/O. Some constructs, especially initialization, are target-dependent rather than universally synthesizable or unsynthesizable.

Worked example

The clocked register below has no simulation delays or host interactions. Its enabled hold behavior is part of the hardware specification. A separate testbench can use printing and delays without placing them in the synthesized DUT.

module synthesizable_reg(input clk,reset,enable,input [3:0] d,output reg [3:0] q);
  always @(posedge clk) begin
    if(reset) q<=0;
    else if(enable) q<=d;
  end
endmodule

What to watch for

A simulator accepting a construct does not establish synthesis support. Conversely, an FPGA-specific initialization feature should not be presented as portable ASIC behavior.

Try it yourself

Is $display a hardware serial output port?

Answer: No. It writes to the simulation host's output. Hardware logging requires an actual implemented interface and associated logic.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.