Your next skill.
Your own pace.

Find your direction in digital design and verification. Explore the learning experience, one subject at a time.

Built for focused learning.

Lessons, practice and progress in one place.

WatchPractiseProgress
Watch the course introduction and review the syllabus before choosing your next subject.

A clear order to learn.

Start with the foundations, then choose design or verification. Equivalent prior knowledge is welcome; the preparation links on each course help you choose your starting point.

Start with the foundations

  1. Digital Electronics
  2. Verilog

Continue into digital design

  1. Advanced Digital IC

Explore the catalogue

Build your foundations. Choose your next subject.

7 courses

Digital foundationsDigital Electronics
COURSE PREVIEW
12 sectionsSelf-paced

Digital Electronics

Build a working understanding of digital hardware by moving from binary information to circuits that store state and follow a specification.

Digital foundationsVerilog
COURSE PREVIEW
12 sectionsSelf-paced

Verilog

Learn to describe digital circuits in Verilog by connecting language constructs to the hardware they represent.

SystemVerilogSystemVerilog Basics
COURSE PREVIEW
10 sectionsSelf-paced

SystemVerilog Basics

Build on your Verilog knowledge to write clear SystemVerilog models and small, self-checking testbenches.

SystemVerilogSystemVerilog Advanced
COURSE PREVIEW
10 sectionsSelf-paced

SystemVerilog Advanced

Develop a reusable verification environment using SystemVerilog language features after completing the class, interface, and simulation foundations.

SystemVerilogSystemVerilog Projects
COURSE PREVIEW
10 sectionsSelf-paced

SystemVerilog Projects

Apply SystemVerilog Advanced through three progressively richer verification exercises: a synchronous FIFO, a round-robin arbiter, and a small ready/valid register peripheral.

Advanced design and verificationAdvanced Digital IC
COURSE PREVIEW
12 sectionsSelf-paced

Advanced Digital IC

Move from working Verilog modules to digital blocks whose architecture, timing, interfaces, and implementation tradeoffs can be explained and measured.

Advanced design and verificationUVM
COURSE PREVIEW
12 sectionsSelf-paced

UVM

Build a reusable SystemVerilog verification environment by understanding each UVM mechanism before combining it with the next.

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