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UVM

Explore 11 sections and 70 subtopics. Choose a subtopic from the index to see its available articles.

UVM

Browse sections and subtopics. Article links appear where published.

Browse UVM topics

01 · UVM Foundations

1.1 · Reusable verification and UVM architectureNo article yet
1.2 · SystemVerilog prerequisitesNo article yet
1.3 · UVM versions and IEEE 1800.2No article yet
1.4 · Library setup and first testNo article yet
1.5 · DUT top and run_testNo article yet

02 · Objects and Components

2.1 · Uvm_object versus uvm_componentNo article yet
2.2 · Sequence items and transactionsNo article yet
2.3 · Component hierarchyNo article yet
2.4 · Constructors and namingNo article yet
2.5 · Registration macrosNo article yet
2.6 · Copy, compare, print and packNo article yet

03 · Factory and Configuration

3.1 · Factory registration and createNo article yet
3.2 · Type overridesNo article yet
3.3 · Instance overridesNo article yet
3.4 · Configuration databaseNo article yet
3.5 · Virtual interface configurationNo article yet
3.6 · Resource database and configuration debugNo article yet

04 · Phases and Objections

4.1 · Build and connect phasesNo article yet
4.2 · Elaboration and simulation startupNo article yet
4.3 · Run phase and runtime phasesNo article yet
4.4 · Extract, check and report phasesNo article yet
4.5 · Objection lifetime and drain timeNo article yet
4.6 · Phase domains and synchronizationNo article yet

05 · Agents and Environments

5.1 · Driver responsibilitiesNo article yet
5.2 · Passive monitoringNo article yet
5.3 · SequencersNo article yet
5.4 · Active and passive agentsNo article yet
5.5 · Environment compositionNo article yet
5.6 · Reset handling in agentsNo article yet

06 · Transaction-Level Communication

6.1 · Ports, exports and implementationsNo article yet
6.2 · Analysis ports and subscribersNo article yet
6.3 · Analysis FIFOsNo article yet
6.4 · Blocking and nonblocking TLMNo article yet
6.5 · Driver-sequencer handshakeNo article yet
6.6 · TLM connectivity debuggingNo article yet

07 · Sequences and Stimulus

7.1 · Sequence body and lifecycleNo article yet
7.2 · Start_item and finish_itemNo article yet
7.3 · Sequence randomizationNo article yet
7.4 · Responses and transaction IDsNo article yet
7.5 · Sequencer arbitrationNo article yet
7.6 · Locks, grabs and prioritiesNo article yet
7.7 · Layered sequencesNo article yet
7.8 · Virtual sequences and virtual sequencersNo article yet

08 · Checking and Coverage

8.1 · Scoreboards and reference modelsNo article yet
8.2 · In-order and out-of-order checkingNo article yet
8.3 · Transaction matchingNo article yet
8.4 · Coverage subscribersNo article yet
8.5 · Protocol assertions with UVMNo article yet
8.6 · End-of-test completeness checksNo article yet

09 · Register Abstraction Layer

9.1 · Register models and mapsNo article yet
9.2 · Registers, fields and memoriesNo article yet
9.3 · Frontdoor and backdoor accessNo article yet
9.4 · Bus adaptersNo article yet
9.5 · Predictors and mirror stateNo article yet
9.6 · Desired versus mirrored valuesNo article yet
9.7 · Register sequences and access policiesNo article yet
9.8 · Register-model reset and synchronizationNo article yet

10 · Reporting and Debugging

10.1 · Verbosity and report severityNo article yet
10.2 · Report actions and catchersNo article yet
10.3 · Topology and factory diagnosticsNo article yet
10.4 · Transaction recordingNo article yet
10.5 · Timeouts and hangsNo article yet
10.6 · Seed reproduction and failure triageNo article yet

11 · Reusable Verification Projects

11.1 · Verification plans and test librariesNo article yet
11.2 · FIFO environment architectureNo article yet
11.3 · Bus-agent integrationNo article yet
11.4 · Multi-agent environmentsNo article yet
11.5 · Reset and error-injection scenariosNo article yet
11.6 · Coverage-driven regressionsNo article yet
11.7 · Performance and reuse pitfallsNo article yet

No articles published yet. Published articles will appear here.

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