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Verilog

Explore 11 sections and 64 subtopics. Choose a subtopic from the index to see its available articles.

Verilog

Browse sections and subtopics. Article links appear where published.

Browse Verilog topics

01 · Language Foundations

1.1 · HDL versus software programmingNo article yet
1.2 · Design, simulation and synthesis flowNo article yet
1.3 · Source files and lexical rulesNo article yet
1.4 · Modules and portsNo article yet
1.5 · Hierarchy and module instantiationNo article yet
1.6 · Verilog versions and portabilityNo article yet

02 · Data and Expressions

2.1 · Nets and procedural variablesNo article yet
2.2 · Four-state logic and unknown valuesNo article yet
2.3 · Vectors, memories and indexingNo article yet
2.4 · Sized literals and signed valuesNo article yet
2.5 · Arithmetic, logical and bitwise operatorsNo article yet
2.6 · Reduction, shifts and concatenationNo article yet
2.7 · Expression widths and signednessNo article yet

03 · Structural and Dataflow Modeling

3.1 · Gate primitivesNo article yet
3.2 · Continuous assignmentsNo article yet
3.3 · Structural interconnectNo article yet
3.4 · Multiplexers and decoders in dataflowNo article yet
3.5 · Drive strengths and tri-state busesNo article yet

04 · Procedural Modeling

4.1 · Initial and always blocksNo article yet
4.2 · Blocking and nonblocking assignmentsNo article yet
4.3 · If, case, casez and casexNo article yet
4.4 · For, while, repeat and foreverNo article yet
4.5 · Named blocks and variable scopeNo article yet
4.6 · Tasks and functionsNo article yet

05 · Simulation Scheduling and Timing

5.1 · Event queues and delta cyclesNo article yet
5.2 · Sensitivity lists and event controlsNo article yet
5.3 · Timescale and simulation delaysNo article yet
5.4 · Intra-assignment versus inter-assignment delaysNo article yet
5.5 · Race conditionsNo article yet
5.6 · Simulation versus synthesis semanticsNo article yet

06 · Combinational RTL

6.1 · Complete assignments and latch avoidanceNo article yet
6.2 · Combinational always blocksNo article yet
6.3 · Priority and parallel selectionNo article yet
6.4 · Arithmetic datapathsNo article yet
6.5 · Parameterizable combinational logicNo article yet

07 · Sequential RTL and FSMs

7.1 · Registers and clock enablesNo article yet
7.2 · Synchronous and asynchronous resetsNo article yet
7.3 · Counters and shift registers in RTLNo article yet
7.4 · FSM state and output codingNo article yet
7.5 · Mealy and Moore RTLNo article yet
7.6 · Pipelining and latencyNo article yet

08 · Reusable and Parameterized Design

8.1 · Parameters and localparamsNo article yet
8.2 · Generate loops and conditional generationNo article yet
8.3 · Parameterized widths and depthsNo article yet
8.4 · Compiler directives and includesNo article yet
8.5 · Configurations and library organizationNo article yet

09 · Memories and Interfaces

9.1 · RAM and ROM modelingNo article yet
9.2 · Memory initializationNo article yet
9.3 · Read latency and read-during-write behaviorNo article yet
9.4 · Synchronous FIFO designNo article yet
9.5 · Ready-valid handshakesNo article yet
9.6 · Simple bus and serial interfacesNo article yet

10 · Testbenches and Debugging

10.1 · Clock and reset generationNo article yet
10.2 · Directed stimulusNo article yet
10.3 · Self-checking reference modelsNo article yet
10.4 · System tasks and file IONo article yet
10.5 · Waveform dumps and debuggingNo article yet
10.6 · Regression tests and corner casesNo article yet

11 · Synthesis and Advanced Modeling

11.1 · Synthesizable and simulation-only constructsNo article yet
11.2 · Resource inference and coding pitfallsNo article yet
11.3 · Lint and synthesis warningsNo article yet
11.4 · Timing constraints and gate-level simulationNo article yet
11.5 · Specify blocks and timing checksNo article yet
11.6 · User-defined primitivesNo article yet

No articles published yet. Published articles will appear here.

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