Arithmetic, logical and bitwise operators in Verilog

Arithmetic operators calculate numeric results. Bitwise operators act on corresponding bits, while logical operators test whether operands are logically true or false and produce a one-bit result. Choosing between & and && changes the question being asked, even when both happen to produce the same value for one-bit inputs.

Worked example

The two vectors have nonzero values but no overlapping set bits. Their bitwise AND is zero, while their logical AND is one because both vectors are logically true. Add widths to expected values when reviewing results.

module example;
reg [3:0] a,b;
initial begin
  a=4'b1000; b=4'b0001;
  $display("bitwise=%b logical=%b",a & b,a && b); // 0000, 1
  $finish;
end
endmodule

What to watch for

A logical operator does not compare every bit pair. Conversely, a bitwise expression used as a condition may conceal which individual bit controls the decision.

Try it yourself

For a=4'b0010 and b=4'b0011, what is a ^ b?

Answer: The bitwise XOR is 0001. Only bit zero differs between the two operands.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.