Simple bus and serial interfaces in Verilog

An interface is more than its pin names. Specify sampling edges, acceptance conditions, response timing and reset behavior before connecting a bus or serial link. A parallel register write and a serial shift register use similar storage but different transaction boundaries. Real protocols add framing, addressing and error rules that must be implemented separately.

Worked example

This parallel write port accepts a byte on a rising edge when write_enable is high. It is a deliberately simple register interface, not an APB, AXI or UART implementation. A testbench should also check idle edges and reset priority.

module write_register(input clk,reset,write_enable,input [7:0] write_data,
                      output reg [7:0] value);
  always @(posedge clk) begin
    if(reset) value<=8'h00;
    else if(write_enable) value<=write_data;
  end
endmodule

What to watch for

A serial receive signal is often asynchronous to the local clock. A shift-register example alone does not supply clock-domain synchronization, baud recovery or framing.

Try it yourself

When is a write accepted by this register?

Answer: At a rising clock edge with reset inactive and write_enable asserted. Values changing between edges do not directly update the register.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.