System tasks provide simulation interaction such as reporting, file access and termination. File I/O can supply vectors or save results, but it is not generally a synthesizable data-source interface. Check file-open and scan results so a missing file does not silently turn a useful test into uninitialized stimulus.

Worked example

The code opens a vector file and verifies that one hexadecimal value was read. Create vectors.txt containing 3a before running it. The result of fscanf is the number of successfully matched fields; one expected field requires a result of one.

Verilog
module example;
integer fd,status;reg [7:0] value;
initial begin
  fd=$fopen("vectors.txt","r");
  if(fd==0) $display("FAIL could not open vector file");
  else begin
    status=$fscanf(fd,"%h",value);
    if(status!=1) $display("FAIL malformed vector");
    else $display("value=%h",value);
    $fclose(fd);
  end
  $finish;
end
endmodule

What to watch for

A simulation task that reads a host file is not a hardware file reader. Real external data must arrive through a modeled interface or a supported initialization flow.

Try it yourself

What should happen when fscanf returns zero for a required vector?

Answer: The test should report malformed input and fail or stop deliberately. Do not proceed as though a new valid vector was received.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.

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