Multiplexers and decoders in dataflow in Verilog

Dataflow modeling expresses selection as equations. A mux chooses one input value; a decoder asserts an output corresponding to a binary code. Document what happens for every selector value and use matching widths. A ternary operator also has defined four-state merging behavior when its condition is unknown.

Worked example

The first equation selects one four-bit word. The second forms a one-hot decode of a two-bit selector. Each binary selector produces one set bit; this is combinational selection, not a clocked state update.

module select_decode(input [3:0] a,b, input choose_b,
                     input [1:0] index, output [3:0] y,decode);
  assign y=choose_b ? b : a;
  assign decode=4'b0001 << index;
endmodule

What to watch for

An unknown selector is not guaranteed to choose a convenient default input. Exercise unknowns in simulation when they are useful for detecting reset or control problems.

Try it yourself

What is decode for index=2'b10?

Answer: It is 4'b0100: the initial one is shifted left by two positions within the four-bit result.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.