Synchronous and asynchronous resets in Verilog

A synchronous reset is sampled at a clock edge. An asynchronous reset can change a register independently of the normal data-sampling edge. Reset choice affects library inference, timing and reset distribution. Asynchronous assertion does not make deassertion automatically safe; reset release must satisfy the relevant timing and clock-domain requirements.

Worked example

The sensitivity list includes the active-low reset edge, so assertion clears q without waiting for a clock. Normal data sampling still occurs only on rising clock edges while reset is inactive.

module async_reset_reg(input clk,reset_n,d,output reg q);
  always @(posedge clk or negedge reset_n) begin
    if(!reset_n) q<=1'b0;
    else q<=d;
  end
endmodule

What to watch for

A reset signal crossing into a clock domain deserves a release strategy. Do not equate an asynchronous-reset coding template with a complete reset-domain-crossing solution.

Try it yourself

Does a synchronous reset change q immediately when reset changes between clock edges?

Answer: No. In a synchronous-reset register, the reset condition is evaluated at the active clock edge.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.