Drive strengths and tri-state buses in Verilog

Tri-state models allow a driver to release a net by driving z. Resolved nets can model a shared external bus, but internal FPGA tri-states are often converted into multiplexing or rejected depending on the target. Driver strengths refine simulation resolution and should not be mistaken for a portable physical current specification.

Worked example

When output_enable is one, the module drives data onto bus. Otherwise it releases the connection. A testbench or another device may drive the bus while it is released; mutually exclusive enables are essential.

module bus_driver(input output_enable, input [3:0] data,
                  inout wire [3:0] bus);
  assign bus=output_enable ? data : 4'bzzzz;
endmodule

What to watch for

Two enabled drivers with conflicting values can resolve to x. Do not use z as a substitute for ordinary internal mux selection without checking target synthesis support.

Try it yourself

What should a disabled shared-bus driver contribute?

Answer: High impedance, so another enabled driver can control the resolved bus. Releasing a bus is different from actively driving zero.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.