Generate loops and conditional generation in Verilog

Generate constructs create hardware structure during elaboration. A genvar loop can instantiate repeated logic, and a constant conditional can include one implementation or another. This is different from a procedural loop or runtime if: the selected structure exists before input stimulus begins.

Worked example

The loop creates WIDTH named bit lanes. Each lane contains one continuous XOR relationship. The generate index is a construction tool, not a counter stored in the synthesized circuit.

module xor_lanes #(parameter WIDTH=4)(input [WIDTH-1:0] a,b,output [WIDTH-1:0] y);
  genvar k;
  generate
    for(k=0;k<WIDTH;k=k+1) begin : lane
      assign y[k]=a[k]^b[k];
    end
  endgenerate
endmodule

What to watch for

A generate condition must be decidable at elaboration. A runtime input cannot create or remove a module instance.

Try it yourself

How many lane blocks exist when WIDTH is four?

Answer: Four elaborated blocks, indexed lane[0] through lane[3]. They are all present concurrently.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.