Registers and clock enables in Verilog

A register samples data at a clock edge and retains it between edges. A clock enable controls whether it accepts a new value on a given edge. In a clocked process, leaving q unassigned on the disabled branch deliberately holds its value; that differs from an incomplete combinational assignment.

Worked example

Reset has priority over enable. When enable is low and reset is inactive, q keeps its previous value. This is the intended register behavior, not an accidental combinational latch.

module enabled_reg(input clk,reset,enable,input [7:0] d,output reg [7:0] q);
  always @(posedge clk) begin
    if(reset) q<=8'h00;
    else if(enable) q<=d;
  end
endmodule

What to watch for

Do not create a new clock with assign gated_clk=clk & enable unless using a correctly designed clock-gating methodology. A data enable and arbitrary combinational clock gating have different timing implications.

Try it yourself

What happens to q at a rising edge with reset=0 and enable=0?

Answer: It retains the previously stored value. The missing else branch expresses a hold in this clocked process.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.