Synchronous FIFO design in Verilog

A synchronous FIFO accepts and removes items in one clock domain. Its correctness depends on accepted operations, not merely requested operations. Define full, empty, simultaneous push/pop behavior and read latency. Keep pointers, count and storage updates consistent, and check boundary cases before generalizing the depth.

Worked example

This two-entry example uses an asynchronous head read and conservatively refuses a push when full, even if a pop is also requested. A pop is accepted only when nonempty. The count changes only when exactly one operation is accepted.

module fifo2(input clk,reset,push,pop,input [7:0] din,
             output [7:0] dout,output full,empty);
  reg [7:0] mem[0:1];reg rd,wr;reg [1:0] count;
  wire take_push=push & !full;
  wire take_pop=pop & !empty;
  assign full=(count==2);assign empty=(count==0);
  assign dout=mem[rd]; // Meaningful only while !empty.
  always @(posedge clk) begin
    if(reset) begin rd<=0;wr<=0;count<=0;end
    else begin
      if(take_push) begin mem[wr]<=din;wr<=~wr;end
      if(take_pop) rd<=~rd;
      case({take_push,take_pop})
        2'b10:count<=count+1'b1;
        2'b01:count<=count-1'b1;
        default:count<=count;
      endcase
    end
  end
endmodule

What to watch for

This is not an asynchronous FIFO, a block-RAM inference template or a fall-through-empty bypass design. Do not cross clock domains with these pointers.

Try it yourself

What happens when a nonempty, nonfull FIFO accepts push and pop together?

Answer: Its count is unchanged, while both pointers advance and the written storage location is updated. Data ordering still needs verification.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.