User-defined primitives in Verilog

A user-defined primitive describes a small logic function with a truth table. Traditional Verilog UDPs have a single scalar output and restricted table syntax; they are different from general modules. Combinational and sequential UDPs have different forms. They are most useful when reading specialized simulation models or learning explicit table semantics.

Worked example

The primitive lists the binary AND truth table. A module wrapper provides a normal top-level circuit and instantiates the primitive. Input combinations not described by a UDP table produce unknown behavior according to the table's rules, so x-state coverage must be designed deliberately.

primitive and_udp(y,a,b);
  output y;input a,b;
  table
    0 0 : 0;
    0 1 : 0;
    1 0 : 0;
    1 1 : 1;
  endtable
endprimitive
module udp_wrapper(input a,b,output y);
  and_udp u0(y,a,b);
endmodule

What to watch for

A UDP is not an arbitrary programmable lookup table with vectors, tasks or nested hierarchy. Review simulation and synthesis support before choosing it for a design flow.

Try it yourself

Can this UDP directly declare an eight-bit output?

Answer: No. Its traditional output is scalar. Use a module and ordinary vector logic for a multi-bit interface.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.