Timescale and simulation delays in Verilog

The timescale directive sets the unit used for delay literals and the precision used for time rounding in affected modules. It controls simulation interpretation, not clock hardware. Keep time conventions consistent across files and specify them near testbench code so a delay value has an unambiguous meaning.

Worked example

With a one-nanosecond unit and one-picosecond precision, #2.5 represents 2.5 ns. The example prints time as a real value to make fractional units easier to inspect. The process is entirely testbench behavior.

`timescale 1ns/1ps
module example;
  initial begin
    #2.5; $display("time in ns=%0.1f",$realtime);
    $finish;
  end
endmodule

What to watch for

Different modules can interpret identical delay literals differently if their time units differ. Avoid depending on implicit compiler defaults or unrelated include-file ordering.

Try it yourself

Does changing timescale change the synthesized maximum clock frequency?

Answer: No. Physical timing comes from the implementation and constraints. timescale changes simulation delay interpretation and precision.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.