Nets and procedural variables

A net represents a connection whose value comes from drivers; a procedural variable holds the value assigned by a process. In ordinary Verilog, wire is used for nets and reg for procedural assignments. These are language categories, not a direct promise that a wire is a metal trace or that a reg is a flip-flop.

Worked example

The variable result is assigned on every activation of the combinational block. The net mirrored is driven by a continuous assignment. Neither declaration introduces clocked state in this example.

module kinds(input a,b, output wire mirrored);
  reg result;
  always @* result = a ^ b;
  assign mirrored = result;
endmodule

What to watch for

Do not assign to a wire with an ordinary procedural assignment. Match the declared object kind to the way it is driven.

Try it yourself

What declaration is needed for a value assigned inside a Verilog always block?

Answer: Normally a procedural variable such as reg. Whether hardware storage is inferred depends on the block, not the keyword alone.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.

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