Event queues and delta cycles in Verilog

A simulator advances through event regions as well as through numeric time. Several updates can occur at the same timestamp while processes react to one another. Zero-time scheduling steps are often informally called delta cycles; ordinary Verilog reasoning must still distinguish active events, nonblocking updates and observation at the end of a time slot.

Worked example

The nonblocking assignment schedules q's update for later in the current time slot. The immediate display sees the previous q. strobe reports the settled value at the end of that slot. Neither statement adds a physical pipeline stage.

module example;
reg q;
initial begin
  q=0; q<=1;
  $display("active q=%b",q); // 0
  $strobe("settled q=%b",q); // 1
  #1;
  $finish;
end
endmodule

What to watch for

Adding #0 is not a reliable general fix for an incorrectly synchronized testbench. It changes scheduling region behavior without expressing a proper sampling contract.

Try it yourself

Can two signal values be observed at different scheduling points with the same $time?

Answer: Yes. Simulation time can remain unchanged while scheduled updates and observations occur within that time slot.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.