Hierarchy and module instantiation in Verilog

Hierarchy is formed by placing module instances inside other modules. Each instance has its own connections and, where present, its own state. Named port connections make the interface easier to review and resist accidental mistakes when a module's port order changes. Hierarchy organizes a circuit; it does not schedule one module after another.

Worked example

The two instances below form parallel AND operations whose outputs feed an OR. Follow the internal wires to draw the corresponding gate network, then verify that the top module computes the intended Boolean expression.

module and2(input a,b, output y);
  assign y=a & b;
endmodule
module combined(input a,b,c,d, output y);
  wire left,right;
  and2 u_left(.a(a),.b(b),.y(left));
  and2 u_right(.a(c),.b(d),.y(right));
  assign y=left | right;
endmodule

What to watch for

A module instance is elaborated hardware. It cannot be conditionally created inside a procedural if statement during simulation.

Try it yourself

How many AND gates does the top-level example contain?

Answer: Two: one for each and2 instance. Both are present at the same time, regardless of their source-code ordering.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.