Modules and ports in Verilog

Modules define reusable hardware boundaries. Ports express the signals that cross a boundary, including their direction and width. In Verilog-2001, ANSI-style declarations keep that information in the module header. An output driven by procedural statements must be declared as a variable, while a continuous-assignment output is normally a net.

Worked example

This mux has two four-bit inputs, a one-bit selection input and a four-bit net output. The conditional operator chooses a value combinationally; the module contains no clock or storage element.

module mux4(input [3:0] a,b, input select_b, output [3:0] y);
  assign y = select_b ? b : a;
endmodule

What to watch for

Port width mismatches may truncate or extend values. Treat width warnings as design information rather than assuming every connection is correct.

Try it yourself

Does output reg automatically mean the module contains flip-flops?

Answer: No. reg means a procedural variable in Verilog. Storage inference depends on the process and whether assignments cover the required conditions.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.