Sized literals and signed values in Verilog

A sized literal states a width and a radix. Signedness controls how a value is interpreted and extended; the same bit pattern can represent different mathematical values. Use explicit widths and signed declarations at arithmetic boundaries so a calculation does not depend on an unexpected unsized integer or unsigned operand.

Worked example

The pattern 1110 is minus two in four-bit two's-complement representation. Assigning it through a signed source to a wider signed destination sign-extends it to 11111110, preserving its mathematical value.

module example;
reg signed [3:0] short_value;
reg signed [7:0] wide;
initial begin
  short_value=4'sb1110; wide=short_value;
  $display("small=%0d wide=%0d bits=%b",short_value,wide,wide); // -2, -2, 11111110
  $finish;
end
endmodule

What to watch for

Writing a hexadecimal literal does not automatically make it signed. A signed destination cannot repair every mixed-signedness expression after evaluation.

Try it yourself

What does 4'hF represent as an unsigned value?

Answer: Fifteen. The four-bit pattern is all ones; interpreting that pattern as signed two's complement would instead give minus one.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.