Lint and synthesis warnings in Verilog

Lint analyzes suspicious source patterns, while synthesis warnings describe issues encountered when interpreting or implementing RTL. Width mismatches, undriven nets, unused signals, multiple drivers and inferred latches are valuable clues. Classify each warning and justify any waiver rather than treating a successful exit code as a clean design review.

Worked example

default_nettype none and explicit widths make this small adder's interface easy to inspect. The example deliberately preserves its carry. Compare tool warnings before and after introducing a misspelled signal or a narrow output in a separate experiment.

`default_nettype none
module checked_add(input [3:0] a,b,output [4:0] sum);
  assign sum={1'b0,a}+{1'b0,b};
endmodule
`default_nettype wire

What to watch for

Suppressing all warnings removes information about potential functional differences. Waivers should identify the exact warning, design intent and reason it is acceptable.

Try it yourself

Should an inferred-latch warning always be ignored because the source uses reg?

Answer: No. reg is a procedural type, not permission to infer unintended storage. Review assignment coverage and the intended circuit.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.