Priority and parallel selection in Verilog

Selection logic can express priority or mutually exclusive alternatives. An if/else-if chain naturally gives earlier conditions priority. If conditions are intended to be mutually exclusive, verify that assumption rather than relying on synthesis to guess it. The resulting hardware structure depends on both the logic and the implementation tools.

Worked example

When both request bits are set, request[1] wins because it is tested first. Defaults define the no-request case. valid distinguishes an actual selection from the default index value.

module priority2(input [1:0] request,output reg valid,index);
  always @* begin
    valid=1'b1;index=1'b0;
    if(request[1]) index=1'b1;
    else if(request[0]) index=1'b0;
    else valid=1'b0;
  end
endmodule

What to watch for

A parallel-looking case statement is not proof that its alternatives cannot overlap when wildcards are used. Review overlap and intended priority explicitly.

Try it yourself

For request=2'b11, what are valid and index?

Answer: Both are one. The higher-priority branch is selected, and valid indicates that a request was present.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.