Counters and shift registers in RTL in Verilog

Counters update a numeric state, while shift registers move stored bits through positions. Both are clocked structures. Define reset, enable and wrap behavior explicitly. A binary counter naturally wraps when its fixed-width addition discards a carry; that is different from a modulo-N counter with a non-power-of-two limit.

Worked example

The counter and shift register update together when enable is asserted. The oldest shift bit is discarded, the new input enters bit zero, and the three-bit counter wraps after seven.

module count_shift(input clk,reset,enable,serial_in,
                   output reg [2:0] count,output reg [3:0] shift);
  always @(posedge clk) begin
    if(reset) begin count<=0;shift<=0;end
    else if(enable) begin
      count<=count+3'd1;
      shift<={shift[2:0],serial_in};
    end
  end
endmodule

What to watch for

Bit ordering determines shift direction. Sketch the old-to-new bit connections rather than relying only on the words left shift or right shift.

Try it yourself

What does the three-bit counter do after count=7 on an enabled edge?

Answer: It wraps to zero. Only three result bits are stored, so the carry beyond bit two is discarded.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.