Specify blocks and timing checks in Verilog

Specify blocks describe module-level timing paths and timing checks for simulation models. They are commonly associated with cell or gate-level modeling, not ordinary synthesizable behavioral RTL. Simulators differ in how much specify syntax and timing-check behavior they implement, and some require explicit options to enable path-delay processing.

Worked example

The example declares an illustrative input-to-output path delay around a buffer equation. The numeric delay is a model parameter, not a characterized library result. With Icarus, specify processing requires its appropriate simulation option; syntax acceptance alone does not prove all timing checks are supported.

`timescale 1ns/1ps
module timed_buffer(input a,output y);
  assign y=a;
  specify
    (a => y) = (2,2);
  endspecify
endmodule

What to watch for

Do not infer setup/hold signoff from an unsupported timing-check task or an unannotated netlist. Confirm the simulator, library models and annotation reports.

Try it yourself

Does putting a path delay in specify insert a physical buffer of that delay during normal RTL synthesis?

Answer: No. It describes simulation timing behavior. Physical timing is determined by the characterized cells, interconnect and implementation.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.