Memory initialization in Verilog

Memory initialization supplies starting contents for simulation and, in some FPGA flows, configuration-time memory contents. readmemh reads hexadecimal words; readmemb reads binary words. File paths are interpreted by the simulation runtime's working directory unless the flow specifies otherwise. ASIC power-up behavior requires a separate implementation strategy.

Worked example

Create words.hex with four lines: 12, 34, 56 and 78. The task loads those values into the four bytes before location two is displayed. This is a file-dependent simulation example; the source alone does not contain the data file.

module example;
reg [7:0] memory [0:3];
initial begin
  $readmemh("words.hex",memory);
  $display("location two=%h",memory[2]); // 56
  $finish;
end
endmodule

What to watch for

Do not confuse simulation initialization with a reset circuit. Whether initialized memory survives synthesis depends on the target and flow.

Try it yourself

What radix does readmemh expect for the data words?

Answer: Hexadecimal. Use readmemb for binary text, and check that file word widths and address ranges match the declared memory.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.