Four-state logic and unknown values in Verilog

Four-state simulation represents 0, 1, unknown x and high-impedance z. Unknowns can reveal uninitialized storage, conflicting drivers or incomplete stimulus. High impedance models a released connection; it is not an ordinary stored Boolean value. Simulation uses these states to expose problems that a purely two-state calculation could conceal.

Worked example

The first display compares an unknown bit with zero using logical equality. The result is x because the comparison is uncertain. Case equality treats x and z as literal simulation states and returns a definite Boolean result.

module example;
reg a;
initial begin
  a=1'bx;
  $display("logical=%b case=%b",a==1'b0,a===1'b0); // x, 0
  $finish;
end
endmodule

What to watch for

Do not replace all comparisons with case equality in synthesizable control logic merely to silence unknowns. Use case equality deliberately in simulation checks.

Try it yourself

What is the value of 1'b0 & 1'bx?

Answer: Zero: the known zero input determines the AND result. An unknown operand does not make every possible expression unknown.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.