Read latency and read-during-write behavior

A memory read interface must specify when data becomes valid and what happens if a read and write target the same address. Different hardware memories support old-data, new-data, no-change or restricted collision behavior. An RTL simulation's apparent result must not be assumed portable to every memory macro or FPGA block.

Worked example

The read output is registered. With nonblocking assignments, q samples the array's old value at the selected address while a write to that address is scheduled for later in the time slot. This describes old-data behavior in RTL simulation.

module sync_ram(input clk,we,input [1:0] address,input [7:0] d,output reg [7:0] q);
  reg [7:0] memory [0:3];
  always @(posedge clk) begin
    if(we) memory[address]<=d;
    q<=memory[address];
  end
endmodule

What to watch for

If the target memory cannot implement the described collision behavior, synthesis may add logic, change inference or warn. Review the memory report and vendor documentation.

Try it yourself

When does q update for a read in this example?

Answer: After the active clock edge, as a nonblocking update. The interface is a synchronous read, not an immediate combinational array lookup.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.

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