Simulation versus synthesis semantics in Verilog

Simulation executes language semantics, whereas synthesis interprets a supported subset as hardware. A construct can be legal and simulate successfully without being synthesizable. Conversely, synthesis can infer intended logic from incomplete simulation descriptions, leaving a simulation/synthesis mismatch that masks a functional defect.

Worked example

This mux uses complete assignments and an automatic combinational sensitivity list. No delay, file access or stimulus generator is included in its RTL. A separate testbench should check every selector and input combination.

module rtl_mux(input sel,a,b,output reg y);
  always @* begin
    if(sel) y=b;
    else y=a;
  end
endmodule

What to watch for

Do not assume simulation x values are physically stored unknowns, or that synthesis interprets every x assignment as a reset value. Optimization and physical behavior are separate concerns.

Try it yourself

What evidence is needed after a design simulates correctly?

Answer: Review synthesis warnings and inferred resources, verify constraints, and check implementation timing. Functional simulation alone does not validate those properties.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.