Expression widths and signedness in Verilog

Expression sizing determines which bits exist during evaluation, not merely which bits are retained at the final assignment. Signedness also propagates through expression rules. Make important arithmetic boundaries explicit by extending operands before addition and by reviewing both operand types and destination widths.

Worked example

The operands are explicitly extended to five bits before addition, so the carry is visible. This example does not rely on subtle context-sizing rules. The resulting value is 10000 rather than the four-bit truncated pattern 0000.

module example;
reg [3:0] a,b;
reg [4:0] sum;
initial begin
  a=4'd15; b=4'd1;
  sum={1'b0,a}+{1'b0,b};
  $display("sum=%b value=%0d",sum,sum); // 10000, 16
  $finish;
end
endmodule

What to watch for

Do not assume the width of a destination explains every intermediate operation, especially across concatenations, casts and mixed signed operands.

Try it yourself

How should you preserve a carry from two unsigned W-bit operands?

Answer: Extend both operands to W+1 bits before adding and store the result in W+1 bits. Then verify maximum-value and boundary cases.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.