Continuous assignments in Verilog

A continuous assignment describes a net driver that remains active during simulation. Its right-hand expression is reevaluated when relevant inputs change. Multiple continuous drivers on one ordinary wire are resolved by net semantics; they are not sequential writes where the last source line wins.

Worked example

The output is an eight-bit inversion of the input. The declaration introduces no procedural variable and no clock. Synthesis can interpret this as a bank of inverters, although optimization may combine it with neighboring logic.

module invert_byte(input [7:0] a, output [7:0] y);
  assign y = ~a;
endmodule

What to watch for

Use continuous assignments for net-driven relationships. A feedback assignment without a deliberate storage model can form a combinational loop rather than a useful register.

Try it yourself

Will y change if a changes long after simulation starts?

Answer: Yes. The continuous assignment remains active; it is not a one-time initialization statement.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.