Ready-valid handshakes in Verilog

A ready-valid interface transfers data only on an edge where both ready and valid are asserted. The source owns valid and data; the destination owns ready. A source must retain a pending item while stalled. Avoid making a source wait for ready before it ever asserts valid, since that can deadlock against a waiting destination.

Worked example

This one-entry register can accept a new word when empty or when its existing word will be consumed. While stalled, input_ready is low and the stored output word and valid bit hold. Reset clears validity rather than requiring every data bit to reset.

module elastic1(input clk,reset,input valid_in,output ready_in,
  input [7:0] data_in,output reg valid_out,input ready_out,
  output reg [7:0] data_out);
  assign ready_in=!valid_out | ready_out;
  always @(posedge clk) begin
    if(reset) valid_out<=1'b0;
    else if(ready_in) begin
      valid_out<=valid_in;
      if(valid_in) data_out<=data_in;
    end
  end
endmodule

What to watch for

The combinational ready path in this small example can become long when many stages are chained. A system interface may require a registered-ready strategy or skid buffer.

Try it yourself

Can the source change a pending data word while valid=1 and ready=0?

Answer: Not under the usual ready-valid contract. It must hold the word and valid until the transfer is accepted.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.