For, while, repeat and forever in Verilog

Procedural loops repeat statements within a process. In synthesizable RTL, a loop with statically bounded iterations often expands into hardware rather than taking one clock cycle per iteration. Testbench while, repeat and forever loops instead control the simulation process and require delays or event controls where time must advance.

Worked example

The four iterations build a combinational OR reduction. result is initialized on every activation before the loop accumulates the input bits. No clock appears, so the loop does not represent four sequential cycles.

module loop_or(input [3:0] a,output reg result);
  integer i;
  always @* begin
    result=1'b0;
    for(i=0;i<4;i=i+1) result=result | a[i];
  end
endmodule

What to watch for

A loop whose exit condition depends on unconstrained runtime values may not be synthesizable. Count cycles with a clocked state machine when the algorithm requires time.

Try it yourself

How many cycles does a four-iteration combinational for loop take?

Answer: It does not define a cycle count. It describes combinational logic; physical propagation delay depends on the synthesized implementation.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.