Initial and always blocks in Verilog

An initial process starts once at the beginning of simulation. An always process repeats according to its event or delay controls. RTL synthesis supports specific patterns within these constructs; testbench initialization and clock generators do not all translate into ordinary portable hardware. Choose a process form based on circuit intent.

Worked example

The always block samples d on each rising clock edge. The accompanying test process supplies the clock and stops the simulation. There is no free-running clock source implied inside the register module itself.

module sampled(input clk,d,output reg q);
  always @(posedge clk) q<=d;
endmodule
module tb;
  reg clk,d; wire q;
  sampled dut(.clk(clk),.d(d),.q(q));
  initial begin clk=0;d=1;#2;clk=1;#1;
    $display("q=%b",q);$finish;end
endmodule

What to watch for

An always block with no event control, delay or terminating behavior can create an infinite zero-time simulation loop.

Try it yourself

How often does an initial block begin?

Answer: Once per elaborated instance at simulation startup. Loops or waits inside it may still make that process last for many simulated cycles.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.