Complete assignments and latch avoidance in Verilog

Combinational outputs need a value on every execution path. If a variable is left unchanged for some input combinations, the description requires its previous value and can infer a latch. A default assignment at the start of the block makes the intended coverage easier to inspect, especially in longer selection logic.

Worked example

The default sets y to zero whenever enable is false. The conditional overrides it when enabled. Every binary input combination therefore has a defined output without retaining a previous result.

module enabled_value(input enable,input [7:0] data,output reg [7:0] y);
  always @* begin
    y=8'h00;
    if(enable) y=data;
  end
endmodule

What to watch for

Do not use y=y as a default in a block intended to be combinational. That explicitly requests retention rather than supplying a value from current inputs.

Try it yourself

What hardware can always @* if(enable) y=data infer?

Answer: A level-sensitive latch, because y must keep its previous value while enable is false. Add the missing assignment if that storage is unintended.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.