Clock and reset generation in Verilog

A testbench must generate the time and edge relationships expected by the DUT. Initialize control inputs, apply reset for a specified interval and release it away from the sampling edge where appropriate. A testbench clock generator is a simulation process; physical clocks come from the board, oscillator or clock-generation circuitry.

Worked example

The clock toggles every five time units, yielding a period of ten. Reset starts asserted and is released at time twelve, away from a rising edge. A fixed end time prevents a free-running clock from keeping the simulation alive forever.

`timescale 1ns/1ps
module example;
  reg clk,reset;
  initial clk=0;
  always #5 clk=~clk;
  initial begin reset=1;#12;reset=0;end
  initial begin #32;$display("reset=%b",reset);$finish;end
endmodule

What to watch for

An uninitialized clock toggled with clk=~clk remains x. Initialize it explicitly before the repeating process begins to rely on it.

Try it yourself

What clock period does always #5 clk=~clk create here?

Answer: Ten nanoseconds: five low plus five high, because the declared time unit is one nanosecond.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.