Vectors, memories and indexing in Verilog

A packed vector groups bits into one integral value. A Verilog memory is an unpacked array of words, with separate indexing for the word and the bit within that word. Declare ranges intentionally and verify bit ordering at interfaces; ascending and descending ranges can both be legal but are easy to connect incorrectly.

Worked example

word contains one byte. mem contains four byte-wide words. The first index selects a memory word, while the second selects bits from that word. The example writes and reads one location without implying a particular physical RAM implementation.

module example;
reg [7:0] word;
reg [7:0] mem [0:3];
initial begin
  word=8'hA6; mem[2]=word;
  $display("word=%h upper=%h bit0=%b",mem[2],mem[2][7:4],mem[2][0]); // a6, a, 0
  $finish;
end
endmodule

What to watch for

An out-of-range memory index is not a useful wraparound mechanism. Define address widths and check array bounds explicitly in a testbench.

Try it yourself

How many storage bits are declared by reg [7:0] mem [0:3]?

Answer: Four words of eight bits, or 32 bits in the language model. The physical implementation depends on the surrounding access logic and target resources.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.