Parameterizable combinational logic

Parameterized combinational logic uses elaboration-time constants to describe a family of circuits. A width parameter changes vector sizes before simulation begins. Design legal parameter ranges and check small boundary cases; a configurable description is only reusable when its assumptions remain true for every supported configuration.

Worked example

The WIDTH parameter controls all data ports. Instantiating this module with WIDTH=16 creates a sixteen-bit mux, not a runtime-selectable mux width. The ordinary ternary expression works for any supported positive width.

module width_mux #(parameter WIDTH=8)(
  input [WIDTH-1:0] a,b,input sel,output [WIDTH-1:0] y);
  assign y=sel ? b : a;
endmodule

What to watch for

WIDTH=0 produces an unintended range rather than a sensible zero-bit datapath. Reject unsupported parameter values in the verification or elaboration flow.

Try it yourself

Can WIDTH be changed by a normal input signal during operation?

Answer: No. It is an elaboration-time parameter. Runtime configuration must be modeled using inputs and actual hardware logic.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.

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