HDL versus software programming

Verilog describes hardware whose processes run concurrently. A module is not a function called once by a processor: its connections and processes remain present throughout simulation. Combinational logic responds to input changes; clocked logic stores values at selected edges. Begin by identifying signals and storage, then describe their relationships.

Worked example

This small AND circuit is active whenever either input changes. There is no instruction that has to call the assignment again. The test process changes the inputs; the continuous assignment recomputes the output after the simulator processes that change.

module example;
reg a, b;
wire y;
assign y = a & b;
initial begin
  a=1; b=0; #1;
  $display("y=%b", y); // 0
  b=1; #1;
  $display("y=%b", y); // 1
  $finish;
end
endmodule

What to watch for

Do not interpret several always blocks as a fixed sequence of software functions. Their interaction follows events and the simulator's scheduling rules.

Try it yourself

Does placing one always block above another make it execute first?

Answer: No. Source order does not establish a portable execution order between concurrent processes. Establish ordering through data dependencies or clocked interfaces.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.

Continue learning

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Next: Design, simulation and synthesis flow

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