Blocking and nonblocking assignments

A blocking assignment updates its procedural destination before the next statement executes. A nonblocking assignment evaluates its right-hand value now and schedules an update for the nonblocking-assignment region. A common RTL discipline is blocking assignments for combinational calculations and nonblocking assignments for clocked state.

Worked example

At a rising edge, a samples d and b samples the old a. Both right-hand expressions are evaluated before their nonblocking updates become visible. The description therefore models two register stages rather than immediately passing d through both variables.

module stages(input clk,d,output reg a,b);
  always @(posedge clk) begin
    a <= d;
    b <= a;
  end
endmodule

What to watch for

Changing these assignments to blocking assignments changes what b observes in this process. Mixing styles carelessly can also create simulation races across processes.

Try it yourself

If old a=0 and d=1 at an edge, what do a and b become?

Answer: After the scheduled updates, a becomes one and b becomes zero. b sampled the previous stage value, not its newly assigned value.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.

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