Structural interconnect in Verilog

Structural interconnect combines modules through internal nets. A correct top-level structure must preserve signal direction, bit widths and intended fanout. One source may feed several loads, but unrelated outputs should not drive the same ordinary RTL signal unless a deliberately resolved multi-driver connection is intended.

Worked example

Two inversions are connected in series through middle. The top-level output therefore follows the input for binary logic values. The example makes connectivity visible without relying on procedural ordering.

module inverter(input a,output y); assign y=~a; endmodule
module two_stage(input a,output y);
  wire middle;
  inverter u0(.a(a),.y(middle));
  inverter u1(.a(middle),.y(y));
endmodule

What to watch for

Accidentally connecting two output ports to the same wire can create contention and x values in simulation. Renaming a wire does not solve ownership of its driver.

Try it yourself

Does a wire between two modules itself add a clock cycle?

Answer: No. Latency is introduced by storage elements or other specified behavior, not by crossing a module boundary.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.