Compiler directives and includes in Verilog

Compiler directives operate on source text before or during compilation. include inserts another file's text, while define and conditional-compilation directives select token sequences. They do not create runtime signals. Keep macro names distinctive and consider compilation-unit ordering so an include does not silently change unrelated modules.

Worked example

The symbolic constant is expanded before the module is elaborated. The guard avoids defining the same header content repeatedly. A real header could be included with an include directive and a configured include search path.

`ifndef CHIPRION_WIDTH_HEADER
`define CHIPRION_WIDTH_HEADER
`define CHIPRION_WORD_BITS 8
`endif
module header_width(input [`CHIPRION_WORD_BITS-1:0] a,
                    output [`CHIPRION_WORD_BITS-1:0] y);
  assign y=a;
endmodule
`undef CHIPRION_WORD_BITS

What to watch for

Macros perform textual substitution without the scope and type rules of parameters. Prefer module parameters for an instance's configurable numeric properties.

Try it yourself

Does a define create a register that can change during simulation?

Answer: No. It changes source processing. A runtime-configurable value must be represented by an input or a state variable.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.