Intra-assignment versus inter-assignment delays

A delay before an assignment postpones when the statement executes and therefore when its expression is evaluated. An intra-assignment delay evaluates the right-hand side before waiting for its update. Blocking and nonblocking forms differ further, so examine both the sampling time and the update time when debugging a timing model.

Worked example

These two testbench processes start together. At time zero the intra-assignment captures d=0, while the delayed statement waits until time five to read d. A third process changes d at time two. The final display shows the different sampled values.

module example;
  reg d,a,b;
  initial begin d=0; #2 d=1; end
  initial begin #0; a = #5 d; end
  initial begin #5; b = d; end
  initial begin #6; $display("a=%b b=%b",a,b); $finish; end
endmodule

What to watch for

The #0 here only orders this controlled demonstration after initialization. It is not an RTL design technique or a recommended synchronization rule for general testbenches.

Try it yourself

Which form samples d before its delay: a = #5 d or #5 a = d?

Answer: a = #5 d samples d before waiting. In #5 a = d, evaluation occurs after the process's delay.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.

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