An arithmetic datapath combines arithmetic units, bit widths and selection controls. Begin with the required numeric range, then choose operand extensions and output widths. Signed versus unsigned interpretation, carry and overflow are separate properties; a carry bit alone does not diagnose signed overflow.

Worked example

Both operands are extended before addition. The subtract operation uses a separate expression with the same explicit width. The five-bit output preserves the unsigned sum range; interpret subtraction results according to the design's chosen numeric convention.

Verilog
module add_sub4(input [3:0] a,b,input subtract,output [4:0] result);
  wire [4:0] aw={1'b0,a};
  wire [4:0] bw={1'b0,b};
  assign result=subtract ? aw-bw : aw+bw;
endmodule

What to watch for

The most significant result bit is not a universal signed-overflow flag. Define the representation and status outputs instead of assigning meanings after the fact.

Try it yourself

What is the maximum unsigned sum of two four-bit operands?

Answer: Thirty: 15+15. It needs five bits, because four bits can represent at most fifteen.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.

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