Combinational always blocks in Verilog

A combinational always block computes outputs from current inputs without waiting for clock edges. Use blocking assignments for local intermediate calculations and assign outputs completely. Treat the block as a combinational network, then check that each intermediate value is defined before a later statement reads it.

Worked example

temporary is assigned before y, so y uses the freshly calculated expression in the same activation. Both variables receive unconditional assignments. An equivalent dataflow description could combine the expressions in one continuous assignment.

module combine(input a,b,c,output reg y);
  reg temporary;
  always @* begin
    temporary=a & b;
    y=temporary | c;
  end
endmodule

What to watch for

Reversing dependent blocking statements can make y use a previous temporary value. Keep calculation ordering explicit and avoid using the output as unintended state.

Try it yourself

Is a combinational always block clocked because it contains procedural statements?

Answer: No. Its event control and assignment coverage define combinational behavior. Procedural syntax is not the same as sequential hardware.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.