Tasks and functions in Verilog

Tasks and functions package procedural behavior. A traditional Verilog function returns a value and cannot consume simulation time; tasks may have multiple outputs and may contain timing controls. Reuse does not automatically mean shared hardware: synthesis can inline separate calls or optimize the resulting logic.

Worked example

The function returns the larger of two byte-wide operands. Its inputs and return width are explicit. The continuous assignment uses the function as an expression, with no hidden clock or delay.

module maximum(input [7:0] a,b,output [7:0] y);
  function [7:0] max8;
    input [7:0] x,z;
    begin max8=(x>z) ? x : z; end
  endfunction
  assign y=max8(a,b);
endmodule

What to watch for

Static versus automatic storage matters for reentrant or concurrent calls in simulation. Do not assume a task's local state is private to every invocation unless declared appropriately.

Try it yourself

Can a traditional Verilog function wait for a clock edge before returning?

Answer: No. Timing controls belong in a task or process. A function computes its return value without advancing simulation time.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.