Verilog

About this course

Learn to describe digital circuits in Verilog by connecting language constructs to the hardware they represent. This proposed course starts with a short digital-design readiness check, then develops modules, four-state values, vectors, operators and procedural modelling in a deliberate order. Combinational and clocked examples establish how assignment choices, widths, signedness and event scheduling affect simulation and inferred hardware.

The later sequence develops reusable hierarchy, parameterised blocks, self-checking testbenches, finite-state machines and small datapaths. Planned exercises use a practical Verilog-2001 baseline that can run with free simulation tools, with synthesis inspection used to expose unintended latches and other modelling mistakes. A final controller-and-datapath project brings implementation, directed tests, waveform debugging and reproducible tool commands into one reviewable design package.

Learning objectives

• Write and connect Verilog-2001 modules with explicit port and signal widths.
• Predict four-state, signedness and expression-sizing behaviour in common RTL constructs.
• Model combinational and sequential hardware without unintended latches or assignment races.
• Build reusable parameterised modules and elaboration-time generated structures.
• Create self-checking testbenches with repeatable stimuli and useful failure messages.
• Implement an FSM and datapath with defined reset and transaction behaviour.
• Run simulation and basic synthesis checks and interpret the resulting diagnostics.

Curriculum

Prerequisites

• Binary representation, Boolean logic and basic combinational circuit design.
• Flip-flops, registers, counters and clock/reset concepts.
• Basic FSM diagrams and an understanding of setup and hold timing.
• Ability to create text files and execute terminal commands.

Course requirements

• A computer with a text editor, terminal and local project folder.
• A Verilog simulator such as Icarus Verilog with working iverilog and vvp commands; use Verilog-2001 language mode for baseline exercises.
• A VCD waveform viewer such as GTKWave, or another compatible waveform inspection tool.
• Access to Yosys or an equivalent Verilog synthesis tool for the supported synthesizable RTL exercises.
• Browser access for reference documentation and optional HDLBits practice; no FPGA board or paid simulator is required.

Who this course is for

• Learners who have completed digital electronics or equivalent study.
• Engineering students beginning RTL implementation.
• Software developers moving into hardware description.
• Verification learners who need a firm understanding of the RTL under test.

Practice projects

Planned exercises for applying the syllabus.

1. Parameterised arithmetic unit and testbench

   Planned exercise: implement a width-configurable arithmetic and selection block, then use a reference calculation and boundary vectors to check results and status flags.

2. Buffered command controller

   Planned capstone: implement a small synchronous buffer and command-processing FSM with a datapath; test reset, full/empty conditions, accepted commands and repeated transactions.

Curriculum references

• HDLBits: Problem sets

  Primary practice-site taxonomy for language, circuit modelling, simulation reading and testbench progression; accessed 18 October 2026.

• Icarus Verilog: Getting Started

  Official reference for compile/run workflow and simulation examples; accessed 18 October 2026.

• Icarus Verilog: Command Line Flags

  Official language-generation options support a deliberate Verilog-2001 baseline; accessed 18 October 2026.

• Yosys: Converting process blocks

  Official synthesis reference connecting procedural RTL to muxes, latches and flip-flops; accessed 18 October 2026.

Course availability

The research-informed outline describes the planned learning sequence. Enrolment, teaching media, dates and fees remain subject to confirmation.

Programme questions