Digital Electronics

About this course

Build a working understanding of digital hardware by moving from binary information to circuits that store state and follow a specification. The proposed sequence begins with number representation, Boolean reasoning and logic minimisation, then develops reusable combinational and sequential building blocks. Each stage connects equations, truth tables, circuit diagrams and timing waveforms so that learners can explain why a design behaves as intended.

Later sections bring timing constraints, finite-state machines, memories and simple datapaths together in complete design exercises. Planned practice includes arithmetic circuits, counters, sequence detectors and a controller-based capstone with explicit reset behaviour and test cases. The emphasis is on sound digital design decisions and clear evidence of correctness, creating a foundation for Verilog, RTL design and subsequent verification study.

Learning objectives

• Convert between number bases and reason about signed range, carry and overflow.
• Derive and simplify Boolean functions from a written requirement.
• Design combinational arithmetic, selection and encoding circuits.
• Construct registers, counters and shift-register circuits with defined reset behaviour.
• Calculate basic register-to-register setup and hold constraints.
• Translate a sequential specification into a Moore or Mealy state machine.
• Integrate a controller, datapath and small memory into a tested digital design.

Curriculum

Prerequisites

• Comfort with basic arithmetic, powers and simple algebra.
• Ability to read tables and follow step-by-step problem statements.
• Basic familiarity with voltage and time is useful; semiconductor device physics is not assumed.

Course requirements

• Access to a computer and a modern browser for circuit exercises and reference material.
• A notebook or diagramming application for truth tables, circuit diagrams and timing sketches.
• Access to a digital logic simulator capable of gates, flip-flops and clocks; a free option is sufficient.
• A way to save circuit files, test vectors and exercise observations locally.

Who this course is for

• Students beginning electronics, electrical engineering or computer engineering.
• Software learners who want to understand hardware computation.
• Learners preparing for Verilog and RTL design study.
• Graduates revisiting digital logic before verification training.

Practice projects

Planned exercises for applying the syllabus.

1. Arithmetic and selection unit

   Planned exercise: specify and assemble a small add/subtract, compare and select unit; verify boundary values and distinguish carry from signed overflow.

2. Programmable timer controller

   Planned capstone: combine a timer datapath, configuration storage and an FSM; document reset, start, completion and repeated-operation tests.

Curriculum references

• MIT OCW: Computation Structures, Spring 2017 calendar

  University reference for the progression from digital abstraction through combinational, sequential, FSM and performance reasoning; accessed 18 October 2026.

• Steve Ward: The Digital Abstraction

  Primary teaching notes supporting voltage encoding, noise margins and functional versus timing specifications; accessed 18 October 2026.

• Steve Ward: Sequential Logic

  Primary teaching notes supporting stored state, clocked components and timing discipline; accessed 18 October 2026.

• HDLBits: Problem sets

  Exercise taxonomy cross-check for arithmetic, minimisation, counters, shift registers and FSMs; not a source of copied exercise text; accessed 18 October 2026.

Course availability

The research-informed outline describes the planned learning sequence. Enrolment, teaching media, dates and fees remain subject to confirmation.

Programme questions