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Digital Electronics

Build a working understanding of digital hardware by moving from binary information to circuits that store state and follow a specification.

12 sectionsSelf-paced learning

About this course

Build a working understanding of digital hardware by moving from binary information to circuits that store state and follow a specification. The proposed sequence begins with number representation, Boolean reasoning and logic minimisation, then develops reusable combinational and sequential building blocks. Each stage connects equations, truth tables, circuit diagrams and timing waveforms so that learners can explain why a design behaves as intended.

Later sections bring timing constraints, finite-state machines, memories and simple datapaths together in complete design exercises. Planned practice includes arithmetic circuits, counters, sequence detectors and a controller-based capstone with explicit reset behaviour and test cases. The emphasis is on sound digital design decisions and clear evidence of correctness, creating a foundation for Verilog, RTL design and subsequent verification study.

Where to start

This is the foundation course. No prior HDL programming is required.

What you’ll learn

  • Convert between number bases and reason about signed range, carry and overflow.
  • Derive and simplify Boolean functions from a written requirement.
  • Design combinational arithmetic, selection and encoding circuits.
  • Construct registers, counters and shift-register circuits with defined reset behaviour.
  • Calculate basic register-to-register setup and hold constraints.
  • Translate a sequential specification into a Moore or Mealy state machine.
  • Integrate a controller, datapath and small memory into a tested digital design.

Course syllabus

12 sections · 60 topics

01. Digital information and number representation5 topics
  1. Bits, words, positional notation and binary, octal and hexadecimal conversion
  2. Unsigned ranges, two's-complement signed values and sign extension
  3. Binary addition and subtraction, including carry versus signed overflow
  4. BCD, Gray code and parity as examples of alternative encodings
  5. Exercise: choose widths and check boundary cases for a small arithmetic specification
02. Boolean logic and gate behaviour5 topics
  1. Logic levels, valid voltage ranges and the purpose of noise margins
  2. AND, OR, NOT, NAND, NOR, XOR and XNOR truth tables
  3. Boolean identities, complements, duality and De Morgan transformations
  4. Translate between verbal requirements, truth tables, expressions and gate diagrams
  5. Exercise: implement the same Boolean function using different gate families
03. Canonical forms and logic minimisation5 topics
  1. Minterms, maxterms and canonical sum-of-products and product-of-sums forms
  2. Karnaugh maps with two, three and four variables
  3. Grouping rules, don't-care conditions and equivalence checking
  4. Factoring logic and comparing gate count with logic depth
  5. Exercise: minimise a specified control function and verify every defined input combination
04. Combinational selection and coding circuits5 topics
  1. Multiplexers and demultiplexers as routing and function-building blocks
  2. Decoders, encoders and priority encoders with valid indicators
  3. Equality and magnitude comparators
  4. Code conversion and display-decoder design
  5. Exercise: build a configurable input selector with explicit priority behaviour
05. Arithmetic circuits and datapath building blocks5 topics
  1. Half adders, full adders and ripple-carry composition
  2. Adder-subtractors and unsigned versus signed comparison
  3. Carry propagation and an introduction to faster carry structures
  4. Shifts, rotates and a small arithmetic logic unit
  5. Exercise: verify an arithmetic unit against a table of operations and overflow cases
06. Latches, flip-flops and stored state5 topics
  1. Feedback and the distinction between combinational and sequential circuits
  2. SR and D latches, transparency and invalid input combinations
  3. Edge-triggered D flip-flops and characteristic behaviour of JK and T devices
  4. Clock enable, synchronous reset and asynchronous reset behaviour
  5. Exercise: predict and simulate storage-element waveforms across clock and reset events
07. Registers, counters and shift structures5 topics
  1. Parallel registers with load, hold and enable controls
  2. Serial and parallel shift registers, shift direction and rotation
  3. Synchronous up/down and modulo-N counters
  4. Ripple counters as a comparison for clocking and propagation behaviour
  5. Exercise: construct a terminal-count timer and check rollover and load priority
08. Timing and reliable synchronous operation5 topics
  1. Propagation and contamination delay through combinational paths
  2. Clock-to-Q, setup and hold requirements for register paths
  3. Critical-path period estimates and the effect of clock skew
  4. Glitches, asynchronous inputs and the purpose and limits of synchronisers
  5. Exercise: analyse a register path and identify setup or hold violations from timing data
09. Finite-state machine design5 topics
  1. State, transitions, outputs and state diagrams from a behavioural requirement
  2. Moore and Mealy output timing and input dependence
  3. State tables, state reduction and binary versus one-hot encoding
  4. Next-state and output logic with defined reset and recovery behaviour
  5. Exercise: design and test an overlapping sequence detector
10. Memories and implementation choices5 topics
  1. Memory depth, word width, address decoding and capacity calculations
  2. ROM lookup functions and RAM read/write interfaces
  3. Register arrays, synchronous reads and read-during-write specification choices
  4. Conceptual comparison of discrete logic, FPGA lookup tables and standard-cell implementation
  5. Exercise: specify and test a small lookup or storage block with a timing diagram
11. Controller and datapath integration5 topics
  1. Partition a sequential task into data operations and control decisions
  2. Register-transfer descriptions, status signals and control signals
  3. Combine an ALU, registers, counters and a state machine
  4. Latency, throughput and an introductory pipeline tradeoff
  5. Exercise: trace a multi-cycle operation and check the controller against its datapath
12. Capstone specification and validation5 topics
  1. Write the programmable timer's interface, state diagram and acceptance cases
  2. Integrate configuration storage, timer registers and control logic
  3. Check reset, load, start, completion and back-to-back operations
  4. Use simulation traces to debug incorrect transitions and terminal counts
  5. Present the circuit, timing assumptions and a concise test-results record

Course requirements

  • Access to a computer and a modern browser for circuit exercises and reference material.
  • A notebook or diagramming application for truth tables, circuit diagrams and timing sketches.
  • Access to a digital logic simulator capable of gates, flip-flops and clocks; a free option is sufficient.
  • A way to save circuit files, test vectors and exercise observations locally.

Prerequisites

  • Comfort with basic arithmetic, powers and simple algebra.
  • Ability to read tables and follow step-by-step problem statements.
  • Basic familiarity with voltage and time is useful; semiconductor device physics is not assumed.

Who this course is for

  • Students beginning electronics, electrical engineering or computer engineering.
  • Software learners who want to understand hardware computation.
  • Learners preparing for Verilog and RTL design study.
  • Graduates revisiting digital logic before verification training.

Practice projects

Apply the topics in sequence through these planned exercises.

  1. Arithmetic and selection unit

    Planned exercise: specify and assemble a small add/subtract, compare and select unit; verify boundary values and distinguish carry from signed overflow.

  2. Programmable timer controller

    Planned capstone: combine a timer datapath, configuration storage and an FSM; document reset, start, completion and repeated-operation tests.

Curriculum references

Primary documentation and teaching resources that inform this learning sequence.

  • MIT OCW: Computation Structures, Spring 2017 calendar

    University reference for the progression from digital abstraction through combinational, sequential, FSM and performance reasoning; accessed 18 October 2026.

  • Steve Ward: The Digital Abstraction

    Primary teaching notes supporting voltage encoding, noise margins and functional versus timing specifications; accessed 18 October 2026.

  • Steve Ward: Sequential Logic

    Primary teaching notes supporting stored state, clocked components and timing discipline; accessed 18 October 2026.

  • HDLBits: Problem sets

    Exercise taxonomy cross-check for arithmetic, minimisation, counters, shift registers and FSMs; not a source of copied exercise text; accessed 18 October 2026.

Course outline and pricing are subject to confirmation before enrolment opens.

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