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Verilog

Learn to describe digital circuits in Verilog by connecting language constructs to the hardware they represent.

12 sectionsSelf-paced learning

About this course

Learn to describe digital circuits in Verilog by connecting language constructs to the hardware they represent. This proposed course starts with a short digital-design readiness check, then develops modules, four-state values, vectors, operators and procedural modelling in a deliberate order. Combinational and clocked examples establish how assignment choices, widths, signedness and event scheduling affect simulation and inferred hardware.

The later sequence develops reusable hierarchy, parameterised blocks, self-checking testbenches, finite-state machines and small datapaths. Planned exercises use a practical Verilog-2001 baseline that can run with free simulation tools, with synthesis inspection used to expose unintended latches and other modelling mistakes. A final controller-and-datapath project brings implementation, directed tests, waveform debugging and reproducible tool commands into one reviewable design package.

Where to start

Build the knowledge in these courses first, or bring equivalent practical experience:

What you’ll learn

  • Write and connect Verilog-2001 modules with explicit port and signal widths.
  • Predict four-state, signedness and expression-sizing behaviour in common RTL constructs.
  • Model combinational and sequential hardware without unintended latches or assignment races.
  • Build reusable parameterised modules and elaboration-time generated structures.
  • Create self-checking testbenches with repeatable stimuli and useful failure messages.
  • Implement an FSM and datapath with defined reset and transaction behaviour.
  • Run simulation and basic synthesis checks and interpret the resulting diagnostics.

Course syllabus

12 sections · 60 topics

01. Digital readiness and the RTL workflow5 topics
  1. Review combinational logic, registers, FSMs and clock/reset assumptions
  2. Hardware concurrency and the distinction between a circuit description and software execution
  3. RTL, behavioural and structural modelling roles
  4. Create, compile and run a minimal Verilog module and testbench
  5. Exercise: map a circuit diagram to module ports and predict its waveform
02. Modules, values and data declarations5 topics
  1. Verilog-2001 module structure, ANSI-style ports and named signals
  2. Nets versus procedural variables and why reg does not necessarily imply a physical register
  3. Four-state 0, 1, X and Z values and their simulation meaning
  4. Sized literals, vectors, bit selects, part selects and array declarations
  5. Exercise: diagnose undeclared signals, width mismatches and unexpected unknown values
03. Expressions, widths and signed arithmetic5 topics
  1. Arithmetic, relational, logical, bitwise, reduction and conditional operators
  2. Operator precedence, concatenation and replication
  3. Expression widths, truncation, extension and unsized literal hazards
  4. Signed declarations, mixed signed/unsigned expressions and shift behaviour
  5. Exercise: predict and simulate boundary-value results before coding an arithmetic function
04. Combinational RTL modelling5 topics
  1. Continuous assignments and combinational always @* processes
  2. Blocking assignments, complete assignments and safe default values
  3. if/else, case and priority versus parallel selection intent
  4. Latch inference from incomplete assignments and the risks of wildcard case matching
  5. Exercise: implement and exhaustively test a mux, decoder and priority encoder
05. Clocked RTL and simulation scheduling5 topics
  1. Edge-sensitive always blocks for registers, counters and shift registers
  2. Nonblocking updates, old-state evaluation and the active/nonblocking scheduling distinction
  3. Blocking versus nonblocking assignment rules and race-producing examples
  4. Synchronous and asynchronous reset models, enable and load priority
  5. Exercise: debug a pipeline and counter whose simulated behaviour disagrees with the intended circuit
06. Hierarchy and reusable parameterised design5 topics
  1. Module instantiation, named port connections and hierarchical composition
  2. Parameters, localparams and width-dependent interfaces
  3. Generate blocks, genvar and elaboration-time structural replication
  4. Procedural loops with static bounds versus generated hardware instances
  5. Exercise: assemble and test a configurable-width arithmetic unit from smaller modules
07. Tasks, functions and simulation utilities5 topics
  1. Functions for reusable calculations and combinational expressions
  2. Tasks for repeated stimulus sequences and procedural control
  3. Scope, arguments and automatic lifetime where appropriate
  4. Simulation-only initial blocks, delays, display messages and file-based vector input
  5. Exercise: organise reusable stimulus and expected-result helpers without placing testbench code in RTL
08. Self-checking testbenches and waveform debugging5 topics
  1. Instantiate the DUT and generate clock, reset and directed input sequences
  2. Check outputs with explicit expected values and case-aware comparisons
  3. Avoid testbench/DUT races through deliberate drive and sample timing
  4. VCD dump generation, waveform inspection and first-failure diagnosis
  5. Exercise: run boundary and repeated-operation cases with pass/fail counts and a timeout
09. FSMs and controller-datapath RTL5 topics
  1. Translate state diagrams into state registers and next-state logic
  2. Verilog localparam state encodings and Moore versus Mealy outputs
  3. Default transitions, illegal-state handling and output assignment completeness
  4. Separate datapath operations, status flags and controller decisions
  5. Exercise: implement a transaction controller and compare state traces with its specification
10. Arrays, memories and synchronous buffers5 topics
  1. Declare and access unpacked arrays of packed Verilog words
  2. Model synchronous writes and explicitly specified read behaviour
  3. Buffer pointers, occupancy tracking and full/empty boundary conditions
  4. Reset and initialisation choices and their implementation dependence
  5. Exercise: verify a small single-clock buffer including overflow and underflow prevention
11. Synthesizable RTL and implementation inspection5 topics
  1. Distinguish synthesizable design constructs from simulation-only stimulus
  2. Run a basic Yosys read, hierarchy, process conversion and check flow
  3. Inspect inferred registers, multiplexers, memories and unintended latches
  4. Review warnings for undriven signals, conflicting drivers and width errors
  5. Exercise: compare simulated behaviour and inferred structure after a deliberate RTL mistake is corrected
12. Capstone implementation and regression5 topics
  1. Specify the buffered command controller's ports, handshake and reset behaviour
  2. Integrate parameterised storage, control state and arithmetic datapath
  3. Create directed tests for empty/full, reset during activity and repeated commands
  4. Run reproducible simulation and synthesis checks and resolve diagnostics
  5. Document module responsibilities, waveform evidence, assumptions and remaining limitations

Course requirements

  • A computer with a text editor, terminal and local project folder.
  • A Verilog simulator such as Icarus Verilog with working iverilog and vvp commands; use Verilog-2001 language mode for baseline exercises.
  • A VCD waveform viewer such as GTKWave, or another compatible waveform inspection tool.
  • Access to Yosys or an equivalent Verilog synthesis tool for the supported synthesizable RTL exercises.
  • Browser access for reference documentation and optional HDLBits practice; no FPGA board or paid simulator is required.

Prerequisites

  • Binary representation, Boolean logic and basic combinational circuit design.
  • Flip-flops, registers, counters and clock/reset concepts.
  • Basic FSM diagrams and an understanding of setup and hold timing.
  • Ability to create text files and execute terminal commands.

Who this course is for

  • Learners who have completed digital electronics or equivalent study.
  • Engineering students beginning RTL implementation.
  • Software developers moving into hardware description.
  • Verification learners who need a firm understanding of the RTL under test.

Practice projects

Apply the topics in sequence through these planned exercises.

  1. Parameterised arithmetic unit and testbench

    Planned exercise: implement a width-configurable arithmetic and selection block, then use a reference calculation and boundary vectors to check results and status flags.

  2. Buffered command controller

    Planned capstone: implement a small synchronous buffer and command-processing FSM with a datapath; test reset, full/empty conditions, accepted commands and repeated transactions.

Curriculum references

Primary documentation and teaching resources that inform this learning sequence.

Course outline and pricing are subject to confirmation before enrolment opens.

Open course workspace